1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to an IC tester that is seamlessly integrated with an IC simulator so that they may be programmed in the same manner to perform similar tests on simulated and real versions of an IC.
2. Description of Related Art
An integrated circuit (IC) designer typically develops a model of an IC and then tests the model using an integrated circuit simulator. When the test indicates the model operates correctly, the designer uses synthesis and mapping tools to convert the model into a set of masks needed to fabricate a real IC. After the IC has been fabricated a test engineer tests the IC using an integrated circuit tester. It would be helpful if an IC tester could perform the same test on the real IC that the simulator performed on the simulated IC. However due to differences in capabilities of simulators and circuit testers and the manner in which they are programmed, an integrated circuit tester often cannot perform the same test on a real IC that a circuit simulator performs on its simulated counterpart.
In an IC simulator, the nature of the IC to be simulated is typically defined by a device model file (a "netlist") written in a hardware description language such as Verilog or VHDL. The device model file describes the circuit as a set of components connected between circuit nodes, with the response of each component being defined by mathematical expressions relating states of component input signals and time (independent variables) to states of component output signals (dependent variables). An input "test bench" file indicates the manner in which the simulated part is to be tested by indicating how signals at various circuit input nodes are to change state over time. As it carries out the test, the simulator repeatedly increments a "time" variable by a small amount, evaluates the response of all components after each time increment, and produces output "change dump" data indicating how the states or values of signals at the various circuit nodes change with time. This data can then be analyzed to determine how the simulated circuit responds to the input signals.
An integrated circuit tester includes a set of pin electronics circuits, each for carrying out test activities at a separate DUT terminal. An IC tester typically organizes a test into a succession of "test cycles" of uniform duration. During each test cycle, each pin electronics circuit can carry out any one of a limited number of test activities at a DUT terminal. Test activities may include, for example, changing the state of a test signal at a DUT input terminal or sampling the state of a DUT output signal at some particular time during a test cycle. Each pin electronics circuit requires an input test vector (an instruction) before the start of each test cycle to indicate the action the pin electronics circuit is to carry out during the test cycle and a time during the cycle at which it is to carry out that action.
An IC tester has several limitations not shared by a simulator that can render it unable to carry out the same test that a simulator can carry out. First, while a simulator can simulate and test an IC model having any number of I/O terminals, an IC tester can access only a limited number of IC pins. Thus the "bounded pin domain" of a tester (its ability to access only a limited number of IC pins) may prevent it from carrying out a test on a large IC that corresponds directly to a test defined by an HDL test bench.
Second, an IC tester may not be able to carry out the same test as a simulator because it has a limited capacity to store test vectors. A test can involve millions of test events. The test bench file input to a simulator can use a relatively compact algorithm to define millions of test events. Although it takes time to execute an algorithm during the simulation, to a simulator, "time" is just a variable to be incremented as the test progresses. Since the simulator does not have to increment "simulated time" until it is ready to do so, the simulator can take all the real time it needs between simulated time increments to execute the algorithm and to carry out the test instructions it generates. An IC tester, on the other hand, operates in real time because test events must occur in real time. The IC tester therefore does not have unlimited time between test events to execute algorithmic instructions as a test proceeds. Therefore, though a test engineer may initially prepare an algorithm indicating how the test of an IC is to proceed, a host computer will typically execute that algorithm before the test starts to produce sequences of instruction (vectors) defining each step of the test. The host computer then writes those vector sequences into high speed memories within the tester. It may well be that the vector sequence needed to define a test a simulator can carry out can be too large for the tester's vector memories. The length of a test that an IC tester can carry out is therefore limited by the size of its vector memories. Thus due to its "bounded data domain", an IC tester may not be able perform tests as long as those that may be performed by a simulator.
Third, an IC tester may not be able to perform a test carried out by a simulator because it cannot carry out test events in real time as frequently as a simulator can in simulated time. An IC simulator can take as much real time as it needs to simulate any sequence of test events with any desired simulated event timing. However an IC tester, which must operate in real time, is limited in how frequently it can change the state of a test signal or sample an IC output signal. Its "bounded time domain" therefore limits the tester's ability to carry out some sequences of test events.
Thus due to its bounded pin, data and time domains, a tester often cannot test a real IC in the same way that a simulator can test an IC model. It is therefore usually not possible to directly convert a test bench file into a set of instructions for an IC tester. Typically a trained IC test engineer must design a separate test for the real IC that takes into account the limitations of the IC tester. The need for a test engineer other than the IC designer to program an IC tester to perform a test that differs from the test performed by a simulator adds much time and expense to the IC development process and also makes it less certain as to whether the real and simulated ICs are truly comparable in performance.
It would therefore be beneficial to provide a system that would allow an IC circuit designer to test both a simulated IC and its real IC counterpart in exactly the same manner.